PCIe Design Verification Lead

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Responsibilities

THE ROLE:

AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of leading a part of the PCIe Design Verification team. In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as... Graphics Cards and VR sets. This team is responsible for the Verification of several critical IP and Sub-Systems as well as the integration of lower level IPs and the Sub-System delivery to SoC. The team is responsible for verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.

THE PERSON:

A successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.

KEY RESPONSIBILITIES: ? Work on functional verification execution from test plan to verification signoff. ? Collaborate with architects and designers to understand the IP features. ? Write/Implement/Review Test Plans. ? Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification. ? Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of Sub-System level IP interoperability. ? Build testbench components as well as developing test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology. ? Conduct and participate in Code Reviews. ? Technical leadership, including block ownership from start to finish and verification sign-off.

PREFERRED EXPERIENCE:
? Strong background in ASIC Design Flow
? Expertise in Design Verification
? Proficient in Verilog and System Verilog
? Experience verifying complex designs using UVM, OVM or VMM
? Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB or Ethernet is a plus
? Experience with verification of Hardware-Firmware interaction is highly desirable
? Strong analytical and problem solving skills with pronounced attention to detail
? Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality

ACADEMIC CREDENTIALS:
? Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Markham

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Qualifications

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process

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